(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to realize electrostatic discharge, (ESD), implantation and metal silicide blocking with the same photolithographic mask, in a CMOS process.
(2) Description of Prior Art
As the features of CMOS devices continue to be scaled down to deep-sub-micron, (less than 0.25 um), reliability concerns, in terms of ESD damage, become paramount. The input and output pins, of integrated circuit devices, such as CMOS devices, have to sustain ESD stress arising from human handling of these devices, which can approach ESD stress levels of about 2000 volts. Therefore ESD protection devices have to be fabricated, simultaneously with the CMOS devices, and placed around the input and output pads of the integrated circuit.
The concept of simultaneously forming an ESD protection device, and CMOS devices, used for either logic or memory applications, is however handicapped by several features needed with the CMOS devices which however can result in difficulties when included in the ESD protection device. For example the lightly doped, source/drain, (LDD), region, used to alleviate hot carrier effects for the CMOS devices, if used in the ESD device can allow undesirable current to be discharged through the LDD peak, resulting in a damaged ESD protection device. In addition the use of metal silicide formation, used to lower performance degrading resistances of CMOS gate, and source/drain regions, can adversely influence the effectiveness of the ESD protection device. This is a result of the drain of the device, covered with metal silicide, being close to the channel region, easily injecting unwanted ESD current into the diffusion/LDD junction.
FIGS. 1-4, schematically describe prior art, or a process sequence in which an ESD implantation region, is simultaneously formed during a CMOS fabrication sequence, however using two specific photolithographic masks for: the creation of an ESD implantation region; and for the subsequent definition of a silicide layer. Briefly, FIG. 1, schematically shows a first portion of P type semiconductor substrate 103, to be used for ESD device region 101, and a second portion to be used for CMOS device 102. P well region 104, field oxide, (FOX), region 105, as well as gate structures 107, on gate insulator layer 106, are also schematically shown in prior art, FIG. 1. After formation of LDD region 108, in CMOS region 102, photoresist shape 109, is formed, using a specific photolithographic mask for subsequent definition of an ESD implantation region. FIG. 2, schematically shows the creation of heavily doped, N type, ESD implantation region 110, formed in areas of ESD device region 101, not protected by photoresist shape 109. After formation of insulator spacers 111, on the sides of gate structures 107, and the formation of heavily doped source/drain regions 112, in CMOS device region 102, P type, substrate contact regions 118, are formed. This prior art is schematically shown in FIG. 3. A low temperature oxide, LTO), layer 113, is then deposited, followed by formation of photoresist shape 114, to be used to define openings 115, in LTO layer 113. Photoresist shape 114, which will allow metal silicide to be selectively formed on exposed regions of silicon, is defined using another specific photolithographic mask, different from the photolithographic mask used previously to define photoresist shape 109, used for definition of the ESD) implantation region. Therefore metal silicide regions 116, shown schematically in FIG. 4, were formed in openings defined using an additional photolithographic mask, when compared to the present invention in which the same photolithographic mask will be employed for the both the definition of an ESD implantation region, and for definition of openings in an LTO layer which in turn allows selective formation of metal silicide regions.
This invention will describe a novel process for simultaneously forming a ESD protection device, with CMOS devices, however alleviating and eliminating the deleterious effects of the ESD current discharged at an LDD peak, and forming a region with lower breakdown voltage under the center of the drain diffusion to discharge the ESD current. Prior art, such as Hsu, in U.S. Pat. No. 5,585,299, as well as Hsu, in U.S. Pat. No. 5,455,444, describe methods of simultaneously fabricating ESD and CMOS devices, however these prior arts need two photolithographic masks to realize the ESD implantation and silicide blocking.
In this invention a metal silicide blocking region is defined as a region blocked from metal silicide formation, thus a region without silicide, where a metal silicide region is defined as a region covered with metal silicide.
It is an object of this invention to fabricate an ESD protective device, simultaneously with the fabrication of other CMOS devices.
It is another object of this invention to form an ion implanted ESD region, for the ESD NMOS protective device, comprised with a lightly doped concentration, and at a depth great enough to contain a subsequent, more highly doped drain region.
It is yet another object of this invention to use a photolithographic mask to form an implanted ESD region, in portions of a drain region located at the periphery of gate structures, completely consuming the portion of LDD region located at the periphery of these gate structures, and with the photolithographic mask protecting a center portion of the drain/source region, from the ESD implantation procedure.
It is still yet another object of this invention to use the same photolithographic mask, previously used for definition of the implanted ESD region, to define a metal silicide shape, directly overlying the portion of the LDD region located between implanted ESD regions.
In accordance with the present invention a method used to realize ESD implantation, and silicide blocking regions, using the same photolithographic mask, in a CMOS process, is described. After formation of gate structures, LDD regions are formed in regions of a semiconductor substrate not covered by the gate structures. A photolithographic mask is used to allow an implanted ESD region to be formed in regions of the semiconductor substrate, at the periphery of the gate structures, with the photolithographic mask protecting a center portion of the LDD region from the ESD implantation procedure. After formation of insulator spacers, on the sides of the gate structures, a heavily doped region, shallower than the implanted ESD region, is formed in a region of the semiconductor substrate not covered by the gate structures, or by the insulator spacers. The same photolithographic mask, previously used to define the implanted ESD region is again used to define openings in a silicon oxide layer, exposing the top surface of the gate structures, and exposing the region of the LDD region, located between gate structures, where the LDD region was protected from the ESD implantation procedure. Metal silicide shapes are selectively formed on these exposed regions, including formation of a metal silicide shape directly overlying the portion of the LDD region, not occupied with the implanted ESD region, and leaving the drain regions, at the periphery of-the gate structures without metal silicide. Metal contact structures are then formed on elements of the ESD protective device, including formation of metal contact structures, to the metal silicide shape, located on an LDD region, between gate structures.